Senior/Principal Full-Chip Physical Verification Engineer
Senior/Principal Full-Chip Physical Verification Engineer
San Jose, CA or Irvine, CA
Celero Communications, Inc. is an exciting and fast-growing semiconductor startup developing high-performance coherent digital signal processors (DSPs) for optical interconnects used in large-scale AI infrastructure. Celero's goal is to enable higher-bandwidth, lower-power optical connectivity between AI clusters and data centers.
We are seeking a Full-Chip Physical Verification Engineer to join our Physical Design team and help deliver complex digital blocks and full-chip implementations in advanced process technologies. This role will own all aspects of Physical Verification execution on advanced TSMC nodes, ensuring design quality, manufacturability, and tapeout readiness.The ideal candidate has successfully completed multiple tapeouts and brings deep expertise in physical verification methodologies, including driving improvements in quality, execution efficiency, and predictable delivery across multiple programs.
You will work closely with the Analog Design and Physical Design teams to identify and resolve verification challenges while ensuring designs meet aggressive performance, manufacturability, and schedule objectives.
Locations: San Jose, CA (preferred) or Irvine, CA (HQ)
Key ResponsibilitiesTeam Project Leadership
Lead full chip Physical Verification effort
Own execution plans, schedules for full-chip
Drive accountability for quality, milestones, and tapeout readiness.
Conduct full chip and blocks PV checks
Physical Verification OwnershipOwnership of full chip verification
Work with internal analog team to ensure clean IP delivery
Responsible for running and analyzing DRC/ERC/LUP/PERC results
Experience with using either ICV or Calibre verification tools
Understanding advance TSMC DRC rules
Cross-Functional CollaborationPartner with analog, block, chip top owners to ensure clean floorplan
Provide early guidance on corner case requirements
Influence floorplan constraints, hierarchy, and implementation strategy
Participate in tapeout readiness reviews
Required QualificationsBachelors or Masters degree in Electrical Engineering or related field.
7+ years of experience with full-chip verificationsProven hands-on experience with: Physical Verification tool (ICV/Calibre)
Able to assemble a flow to support block/chip level PVStrong expertise in: Floorplanning to avoid DRC/LVS issues
Provide guidance to analog IP team to allow for clean integration
Preferred QualificationsExperience in advanced technology nodes (7nm, 5nm, 3nm)
Automation skills using Tcl, Python, or shell scripting
Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location)