Synopsys Jobs in California
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Search Results - Synopsys Jobs in California
Synopsys Inc-Sunnyvale
At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything.
And we’re...
mindmatch.ai -
Ursus, Inc.-San Jose
JOB TITLE: STA Physical Design Engineer
LOCATION: San Jose, CA (hybrid 3-4 days onsite)
DURATION: 6+ Months
PAY RANGE: $80-$110/hr
TOP 3 SKILLS:
• 8-10+ years' experience in Physical Design and STA
• Expert in Synopsys timing analysis tool...
resume-library.com -
Synopsys Inc-Sunnyvale
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything.
And we’re...
mindmatch.ai -
HireTalent-Mountain View (CA)
constraints, and porting this setup to new technology nodes. Experience with either Synopsys Fusion Compiler or Design Compiler is required.
" This candidate should be comfortable with maintaining tool setup/automation scripts in TCL
" We're committed...
resume-library.com -
Synopsys Inc-Sunnyvale
is between $146,000-$200,000 In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package...
mindmatch.ai -
Leadstack Inc-San Jose
including synthesis, timing analysis, and formal verification.
• Expert usage of Synopsys timing analysis tool Primetime.
• Execute timing ecos using Synopsys and other industry-standard tools.
• Utilize scripting languages such as TCL, Perl...
resume-library.com -
Leidos-National City (CA)
and flows (Synopsys, Cadence, etc.)
• Microelectronics hardware subject matter expertise in at least (1) of the areas listed below AND experience in (1) additional area listed below:
• Microelectronics Supply Chain: microelectronics hardware verification...
8 similar jobs: Cardiff By The Sea, Petersburg, Rancho Santa Fe, San Diego, La Jolla...
Experis-San Jose
UVM working/debug background knowledge
Bonus points if:
• Proficient with System Verilog/Verilog RTL source code
• Proficient with Synopsys Design Compiler and/or Design Compiler Ultra
• Python, tcl and other typical scripting languages...
Leidos-La Jolla
for lab testing
Preferred Qualifications
• Masters degree in Electrical or Computer Engineering
• Experience with DSP fundamentals and FPGA implementation
• Experience with Matlab/Simulink
• Experience with microchip EDA tools and flows (Synopsys, Cadence...
8 similar jobs: Chula Vista, Arlington, El Cajon, Cardiff By The Sea, National City...
Western Digital-Roseville
EDA tools for synthesis, place and route, and timing analysis (e.g., Cadence, Synopsys).
• Deep understanding of digital design principles, including FSMs, data path architectures, and low power design techniques.
• Good understanding of physical...
Leidos-El Cajon
with DSP fundamentals and FPGA implementation
• Experience with Matlab/Simulink
• Experience with microchip EDA tools and flows (Synopsys, Cadence, etc.)
• Microelectronics hardware subject matter expertise in at least (1) of the areas listed below...
6 similar jobs: Rancho Santa Fe, La Jolla, San Diego, Cardiff By The Sea, Chula Vista...
Carlsbad
and coding guidelines, participate in code reviews and accept feedback
• Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify, etc.
• Demonstrated ability to design...
viasat.com -
Arm Limited-San Jose
Experience in leading datacenter SOCs is a plus.
• Experience with Cadence, and/or Synopsys DFT and simulation tools
Salary Range:
From:$283,305
To: $383,295
In Return:
At Arm, we are proud to have a set of behaviors that reflect our culture and guide...
appcast.io -
LanceSoft, Inc.-San Diego
Principal Duties & Responsibilities :
• Implement Hierarchical blocks of the DDR/system cache subsystem running the physical synthesis with Synopsys Fusion Compiler.
• Work with RTL designers on managing complex power intent
• Manage timing...
mindmatch.ai -
LanceSoft Inc-San Diego
the physical synthesis with Synopsys Fusion Compiler.
" Work with RTL designers on managing complex power intent
" Manage timing constraints
" Trouble shoot upf issues in synthesis
" Run Conformal Low Power Checks on final netlist and resolve clp violations...
resume-library.com -
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