Principal Semiconductor Engineer
Artech LLC | Plymouth | www.resume-library.com |
Job Title: Principal Semiconductor Engineer
Location: 12001 State Highway 55, Plymouth, MN, 55441
Duration: 6 months
Description:
Looking for Integrated Circuit Physical Design to work onsite in Plymouth MN and with secret level clearance.
Key Responsibilities
Lead efforts to translate customer designs into Client’s ASIC technology (RTL to GDSII)
Execute and address Floor-planning, Power grid design and deployment, achieve timing closure complying to timing constraints, harmonize DFT-insertion needs with physical design needs, configure for and pass physical verification requirements
Execute design work fully on-site when required (e.g., Classified Designs)
Present and participate in project phase gate reviews
Prepare Documentation
Mentor junior engineers
Tools We Use:
Synopsys Design Compiler
Synopsys PrimeTime
Synopsys DFT Compiler
Synopsys IC Compiler
Synopsys TetraMAX
Siemens Tessent MemoryBIST
Ansys Redhawk
Synopsys IC Validator
Siemens Calibre
You Must Have:
Degree in Electrical Engineering or Computer Engineering
5 years of ASIC Physical Design experience
Ability and willingness to work on-site at the Client Plymouth, MN facility (zip code 55441)
US Citizenship is required
Dual Citizenship is not allowed due to contractual requirements
Previously held USG Secret security clearance in good standing, or, no known barriers to achieve a USG Secret security clearance is required
We Value:
5 or more years of experience with digital IC design using Synopsys EDA tools
Strong scripting language skills – e.g., Perl, Shell, TCL, C
Strong technical problem-solving skills
Windows OS and LINUX OS and Client office suite tools proficiency
Effective and clear communication skills and good ability to work with others
Work accurately with excellent attention to detail
Ability to work simultaneously on multiple projects and follow up on responsibilities
Self-starter who requires minimal oversight
Experience with Siemens Physical Verification tools and methods
Radiation effects analysis knowledge/experience
Advanced node and SOI CMOS technology design experience
Regards,
Pradeep V
Artech Information Systems LLC
(602) 325- 6670 | Fax: (phone number removed) I Text : (phone number removed)
Location: 12001 State Highway 55, Plymouth, MN, 55441
Duration: 6 months
Description:
Looking for Integrated Circuit Physical Design to work onsite in Plymouth MN and with secret level clearance.
Key Responsibilities
Lead efforts to translate customer designs into Client’s ASIC technology (RTL to GDSII)
Execute and address Floor-planning, Power grid design and deployment, achieve timing closure complying to timing constraints, harmonize DFT-insertion needs with physical design needs, configure for and pass physical verification requirements
Execute design work fully on-site when required (e.g., Classified Designs)
Present and participate in project phase gate reviews
Prepare Documentation
Mentor junior engineers
Tools We Use:
Synopsys Design Compiler
Synopsys PrimeTime
Synopsys DFT Compiler
Synopsys IC Compiler
Synopsys TetraMAX
Siemens Tessent MemoryBIST
Ansys Redhawk
Synopsys IC Validator
Siemens Calibre
You Must Have:
Degree in Electrical Engineering or Computer Engineering
5 years of ASIC Physical Design experience
Ability and willingness to work on-site at the Client Plymouth, MN facility (zip code 55441)
US Citizenship is required
Dual Citizenship is not allowed due to contractual requirements
Previously held USG Secret security clearance in good standing, or, no known barriers to achieve a USG Secret security clearance is required
We Value:
5 or more years of experience with digital IC design using Synopsys EDA tools
Strong scripting language skills – e.g., Perl, Shell, TCL, C
Strong technical problem-solving skills
Windows OS and LINUX OS and Client office suite tools proficiency
Effective and clear communication skills and good ability to work with others
Work accurately with excellent attention to detail
Ability to work simultaneously on multiple projects and follow up on responsibilities
Self-starter who requires minimal oversight
Experience with Siemens Physical Verification tools and methods
Radiation effects analysis knowledge/experience
Advanced node and SOI CMOS technology design experience
Regards,
Pradeep V
Artech Information Systems LLC
(602) 325- 6670 | Fax: (phone number removed) I Text : (phone number removed)
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