Packaging Designer Jobs in San Diego
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Search Results - Packaging Designer Jobs in San Diego
Pitaya Foods-San Diego
to join our team and contribute to the development of effective packaging designs. Open to part-time availability (will likely turn into a full-time position).
Job Description:Were seeking a creative and detail-oriented Graphic Designer to join our team...
mindmatch.ai -
Leidos-San Diego
packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip interconnect (chiplet, flipchip, wire/ribbon bonding), modeling & simulation (power, speed, timing, signal integrity, thermal...
Orora Packaging Solutions-San Diego
and product training
2. Work with one of the largest and most innovative team of graphic & structural packaging designers in the industry
3. Dedicated customer service and global sourcing teams
4. In-house testing lab with ability to validate ecommerce...
mindmatch.ai -
Leidos-San Diego
packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip interconnect (chiplet, flipchip, wire/ribbon bonding), modeling & simulation (power, speed, timing, signal integrity, thermal...
Murata Manufacturing Co., Ltd.-San Diego
devices.
• Detailed product packaging design including use of simulation tools to assess design integrity and performance such as modeling of parasitic losses, thermal dissipation, mechanical stress etc.
• Guide design team what they should do or not based...
appcast.io -
Leidos-San Diego
speed, timing, signal integrity, thermal, reliability, etc.)
• Chip-Scale Design: digital, RF and/or mixed signal device packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip...
Leidos-San Diego
packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip interconnect (chiplet, flipchip, wire/ribbon bonding), modeling & simulation (power, speed, timing, signal integrity, thermal...
leidos.com -
Leidos-San Diego
ANSYS Parametric Design Language, APDL), maintaining APDL macros/workflows, establishing FEA methodologies for test correlation, material characterization, and performing stress/mechanical analysis for board package designs and failure prediction...
Leidos-San Diego
speed, timing, signal integrity, thermal, reliability, etc.)
• Chip-Scale Design: digital, RF and/or mixed signal device packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip...
leidos.com -
San Diego
for package design improvements
• Assist warehouse manager with supply chain and logistics when needed
Qualifications:
• Bachelor’s degree preferred. Work experience may be a substitute for secondary education.
• Experience in a high-growth, multi-location...
icims.com -
Leidos-San Diego
packaging design/layout (2D-3D, chiplet/UCIe), substrate/interposer design (HDI, HDBU, EMIB), chip attach (epoxy, solder), chip interconnect (chiplet, flipchip, wire/ribbon bonding), modeling & simulation (power, speed, timing, signal integrity, thermal...
leidos.com -
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