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Physical Design Jobs in San Jose

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Search Results - Physical Design Jobs in San Jose
apartmentCentral Business SolutionsplaceSan Joseevent_available
Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either...
apartmentBroadcomplaceSan Joseevent_available
Overview As a Physical IC Design Engineer at Broadcom, you will drive RTL-to-tape-out for PCIe switch and enterprise storage products within the Data Center Solutions Group. You will work on high-performance silicon and collaborate with RTL...
apartmentApetan ConsultingplaceSan Joseevent_available
Position: Physical Design Engineer – Lead Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do:  •  Drive ASIC physical design implementation from floorplanning through signoff.  •  Perform Place & Route (PnR), Clock Tree Synthesis...
apartmentGoogleplaceSan Joseevent_available
Overview In this role you lead end-to-end physical design for top CPU blocks, driving innovative methodologies and AI/ML-augmented flows to maximize PPA. You will shape technical roadmaps, mentor peers, and influence architectural trade-offs...
apartmentSamsung-SemiconductorplaceSan Joselanguageappcast.ioevent_available
and collaborate with architects and verification engineers to ensure robust designs. You will work with physical design on timing, synthesis, DFT, and STA, shaping product roadmaps for memory and storage solutions in a collaborative, innovation-driven #J-18808...
apartmentNvidiaplaceSan Joseevent_available
Overview As an ML/AI Physical Design Methodology Engineer, you will engineer ML-driven approaches to optimize production physical design flows. You’ll help push the boundaries of PPA through data-driven methods and contribute to flow, tool...
apartmentSiMa.ai, Inc.placeSan Joselanguageappcast.ioevent_available
collaborates with verification, physical design, architecture, and firmware teams to achieve timing, power, and area targets, with emphasis on high-quality, synthesizable RTL and DFT readiness. #J-18808-Ljbffr...
apartmentIntelplaceSan Joseevent_available
Overview In this role you will drive the physical implementation of state-of-the-art GPU designs, from RTL to GDS, focusing on performance, power, and area. You will work within the Data Center Group to optimize GPUs and develop scalable design...
apartment1000 Micron Technology, Inc.placeSan Joselanguageappcast.ioevent_available
The role emphasizes collaboration with verification, physical design, and system teams, with opportunities to use AI-assisted tools to boost engineering efficiency and produce production-grade designs. #J-18808-Ljbffr...
apartmentGoogleplaceSan Joseevent_available
Overview As an ASIC Physical Design Engineer, you shape AI/ML hardware acceleration by delivering cutting-edge TPU technology at scale. You’ll work across RTL-to-GDSII flows, collaborating with RTL, DFT, floorplanning, and signoff teams...
apartmentSamsung Electronics Co., Ltd.placeSan Joseevent_available
timing and area. /n  •  Produce quality RTL on schedule meeting PPA goals /n  •  Engage with performance and power team on achieving performance and power goals. /n  •  Work with the physical design and CAD team to resolve implementation level details. /n...
apartmentNvidiaplaceSan Joseevent_available
with competitive benchmarks to inform trade-offs Key requirements  •  Master’s in Electrical Engineering or related field; 5+ years of experience  •  Strong background in advanced-node silicon design and physical-design methodology  •  Ability to analyze physical...
apartmentSamsung SemiconductorplaceSan Joseevent_available
and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm).  •  Optimize SRAM designs for performance, power and area (PPA) and yield.  •  Develop custom layouts and perform physical design verifications (e.g., DRC, LVS).  •  Evaluate trade-offs...
apartmentAmazonplaceSan Joseevent_available
Overview You will design and optimize ASIC hardware for data centers, supporting AWS Inferentia and Trainium systems. You’ll collaborate with RTL/Arch and fellow PD engineers to evaluate trade-offs and drive physical implementation from synthesis...
apartmentRenesas ElectronicsplaceSan Joseevent_available
Physical Design Support: Support IC floorplanning and work closely with layout engineers to ensure robust analog layout implementation.  •  Silicon Validation: Analyze silicon measurement results, conduct lab evaluation, and drive necessary design...
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